Inside the Embedded Chip: How Semiconductor Technology Is Reshaping Microcontrollers and Edge SoCs

Most conversations about semiconductors in 2026 are conversations about artificial intelligence accelerators. That is where the revenue growth, the capital expenditure and the headlines are. But the overwhelming majority of chips shipped each year do something far less glamorous: they sense a temperature, close a control loop, drive a motor, encrypt a firmware update, or keep a braking system deterministic for fifteen years in an environment that swings from −40 °C to 150 °C.

These are embedded semiconductors — microcontrollers (MCUs), application-class system-on-chip (SoC) devices, mixed-signal front ends, power devices and the memory that sits alongside them. Their design constraints are almost the inverse of the data centre's. Cost is measured in cents, power in microamps, and product lifetimes in decades. Yet the technology base under them is changing more rapidly than at any point since the 32-bit transition: the memory that has defined the MCU for thirty years is running out of scaling headroom, instruction-set architecture is no longer a settled question, machine learning is migrating into parts with kilobytes of RAM, and packaging is starting to substitute for lithography.

This article is written for embedded engineers, hardware and firmware architects, procurement and supply-chain professionals, product managers, and technical decision-makers who need an accurate, non-promotional picture of where embedded silicon actually stands — what is in production, what is credible but early, and what remains a forecast. Readers will finish with a working understanding of embedded node economics, the non-volatile memory transition, the Arm/RISC-V split, edge AI silicon, chiplet integration, mature-node supply dynamics, and the safety and cybersecurity regulation that increasingly dictates silicon feature lists.

Executive summary

Embedded chips are dominated by mature process nodes (roughly 22 nm to 180 nm), where the design constraints are analogue integration, temperature robustness, non-volatile memory and cost — not transistor density.
Embedded NOR flash has effectively stopped scaling below about 28 nm, forcing a transition to embedded MRAM and RRAM for advanced-node microcontrollers. This is the single most consequential technical shift in the MCU roadmap.
RISC-V has moved from evaluation to design-in in embedded and automotive roles, but Arm remains dominant for application-class embedded processing. A dual-architecture future is now the mainstream industry expectation rather than a fringe forecast.
Edge AI is becoming a segmentation axis for MCU and MPU families, with neural processing units (NPUs) appearing alongside conventional cores. Benchmarks remain fragmented and vendor TOPS figures are poor predictors of delivered performance.
Chiplets are entering automotive through initiatives such as imec's Automotive Chiplet Program and the UCIe standard, but multi-vendor interoperability at production scale is a late-decade proposition, not a 2026 one.
Headline semiconductor market growth is misleading for embedded buyers. World Semiconductor Trade Statistics projected roughly USD 1.5 trillion in 2026 global sales, but that growth is overwhelmingly memory- and AI-driven; MCU, analogue and discrete segments follow a different cycle.
Regulation is now a silicon requirement. The EU Cyber Resilience Act's reporting obligations apply from 11 September 2026 and its main obligations from 11 December 2027, alongside established functional-safety standards such as ISO 26262 and IEC 61508.
Supply-chain strategy has become part of architecture. Node availability, second-source options and long-term supply commitments increasingly determine which silicon a design can safely use.

Why embedded silicon is a different business from leading-edge logic

The public narrative of semiconductors is a narrative of shrinking. Embedded systems have largely opted out of it, for defensible engineering and economic reasons.

First, analogue and high-voltage circuitry does not scale well. An MCU that drives a motor, reads a strain gauge or supervises a battery pack contains amplifiers, converters, comparators and I/O drivers whose performance depends on device physics that improve little — or degrade — at smaller geometries. These functions occupy silicon area that does not shrink proportionally with digital logic.

Second, qualification cost dominates. An automotive part qualified to AEC-Q100 Grade 0 or a medical device controller certified under IEC 60601 carries years of validation. Moving to a new node restarts much of that work, with limited functional payoff.

Third, lifetime supply matters more than performance. Industrial and automotive customers expect production availability for ten to twenty years. That expectation favours stable, well-depreciated process lines.

The practical result is a bifurcated industry. Leading-edge nodes serve AI, mobile and high-performance computing. Embedded systems overwhelmingly consume mature nodes — and the strategic risks in that half of the industry are different, as the US Bureau of Industry and Security documented in its December 2024 public report on mature-node semiconductor use, which examined dependence on foreign foundries across aerospace, automotive, industrial and medical supply chains.

Table 1 — How embedded silicon differs from leading-edge logic

Dimension	Leading-edge logic (AI, mobile)	Embedded silicon (MCU, edge SoC)
Typical node	2–5 nm	22–180 nm; 16/12 nm at the high end
Primary constraint	Density, thermal budget, memory bandwidth	Cost, standby power, analogue integration, temperature
Non-volatile memory	External NAND/NOR, no on-die NVM	On-die eFlash, increasingly eMRAM/RRAM
Product lifetime	2–4 years	10–20 years
Dominant cost driver	Wafer cost and packaging	Test, qualification, package pin count
Key certifications	Rare	ISO 26262, IEC 61508, AEC-Q100, IEC 62443
Volume economics	High ASP, moderate volume	Low ASP, very high volume

The memory wall inside the microcontroller

A microcontroller is defined by its non-volatile memory. Firmware lives on-die, and that memory has for decades been embedded NOR flash (eFlash).

eFlash has reached a well-documented technical and economic ceiling. Below roughly 28 nm, its bit-cell scaling, mask-layer count and voltage requirements make it increasingly impractical to integrate with baseline CMOS logic. Foundries have consequently converged on alternatives at advanced nodes, principally spin-transfer-torque magnetoresistive RAM (eMRAM) and resistive RAM (RRAM), both of which are fabricated in the back end of line and therefore add fewer mask steps to a logic process.

This is not a speculative transition. Published work at the VLSI and ISSCC circuit conferences has demonstrated production-oriented eMRAM macros at 22 nm with random read access in the single-digit nanoseconds and operation at elevated junction temperatures suitable for high-end MCU use. Foundries including GlobalFoundries, TSMC, Samsung and UMC have offered or announced embedded MRAM or RRAM options, and IDMs such as Renesas have published eMRAM test-chip results for sub-22 nm processes.

The engineering trade-offs are real and should not be glossed over:

Retention versus endurance. eFlash remains an excellent data-retention technology in harsh thermal environments. eMRAM offers far higher write endurance but has historically faced retention challenges at extreme temperature, requiring careful bit-cell and error-correction design.
Density and cost. At mature nodes, eFlash is cheaper. The crossover favours eMRAM/RRAM only at 22 nm and below, which is why the majority of shipping MCUs still use eFlash.
System architecture changes. Non-volatile memory with SRAM-like access enables new power strategies — instant-on behaviour, aggressive state retention during shutdown — that firmware architectures have not fully exploited.

Callout — What this means for design teams If your roadmap includes a jump to 22 nm or below for a firmware-heavy controller, assume eFlash is not available and plan for eNVM characteristics that differ in write timing, wear behaviour and error-correction requirements. Validate retention at your worst-case junction temperature rather than relying on datasheet typicals.

Table 2 — Embedded non-volatile memory options (indicative characteristics)

Technology	Node availability	Relative write endurance	Strengths	Principal limitations	Maturity
Embedded NOR flash	~180 nm to 28 nm	Moderate	Proven retention in harsh environments; lowest cost at mature nodes	Poor scaling below 28 nm; high mask adder	Very mature, in volume
Embedded STT-MRAM	28 nm to 12 nm and below	High	Back-end-of-line integration; fast writes; strong endurance	Retention at high temperature; magnetic-field sensitivity considerations	Production at selected foundries
Embedded RRAM	40 nm to 22 nm	Moderate to high	Simple cell; low-cost adder	Variability and read-window management	Production in selected products
FeRAM	Mature nodes	Very high	Extremely low write energy	Limited density; narrower foundry support	Niche production
Off-die NOR/NAND	Any	n/a	Unlimited capacity scaling	Board area, latency, security exposure	Very mature

Figures are indicative and vary substantially by foundry process and product qualification. Validate against the specific process design kit.

Instruction-set architecture: from monoculture toward a dual-architecture market

For most of the past two decades, embedded 32-bit computing meant Arm. That is changing, though more slowly and less absolutely than either enthusiasts or sceptics suggest.

RISC-V, an open instruction-set architecture originating from research at the University of California, Berkeley, has moved from experimental use into production design-in. The clearest evidence is institutional rather than technical: Quintauris, a Munich-based joint venture backed by Bosch, Infineon, Nordic Semiconductor, NXP, Qualcomm and STMicroelectronics, exists specifically to define reference architectures and accelerate automotive-grade RISC-V adoption. Infineon has publicly committed to extending its AURIX automotive MCU line with a RISC-V family and has demonstrated pre-silicon toolchain support for it. RISC-V International has reported annual core shipments approaching the billions, though such aggregate figures should be treated as directional rather than audited.

Two qualifications matter for practitioners:

Ecosystem maturity is uneven. Compiler support (GCC, LLVM), RTOS support (Zephyr, FreeRTOS) and debug tooling are solid for deeply embedded work. Safety-certified toolchains, AUTOSAR integration, and mature middleware are narrower and vendor-specific.
Openness is not the same as portability. RISC-V's extensibility permits vendor-specific custom instructions, which can fragment software portability — precisely the problem an open ISA is often assumed to solve.

The reasonable consensus among analysts and silicon vendors is a dual-architecture market: Arm retaining dominance in application-class embedded processing, and RISC-V growing fastest in cost-sensitive, customisable and deeply embedded roles, including safety-relevant control.

Edge AI: the new segmentation axis

Machine-learning inference has moved down the compute stack into parts that would previously have been considered too small for it. Two distinct approaches coexist.

Software-only inference on general-purpose cores. Quantised models — typically 8-bit integer — running via frameworks such as TensorFlow Lite for Microcontrollers or vendor DSP libraries. This works for keyword spotting, anomaly detection, predictive maintenance and simple vision tasks within tens to hundreds of kilobytes.

Dedicated neural processing units. Fixed-function or programmable accelerators integrated alongside the CPU, offering an order-of-magnitude improvement in inferences per joule for supported operator sets.

The practical difficulty is evaluation. Vendor-quoted TOPS (tera-operations per second) figures describe peak arithmetic throughput under ideal conditions and correlate weakly with delivered application performance, which depends on memory bandwidth, operator coverage, quantisation support and compiler quality. MLPerf Tiny, maintained by MLCommons, is the most credible independent benchmark suite for this class of device, though its workload coverage is narrower than real deployments.

Callout — Evaluating edge AI silicon Benchmark your own quantised model, not the vendor's. Measure end-to-end latency and energy per inference, including memory access and pre-processing. Confirm that every operator in your graph is accelerated; a single unsupported operator falling back to the CPU can eliminate the accelerator's advantage.

Chiplets and advanced packaging: real, but earlier in automotive than in production

As monolithic integration becomes more expensive at advanced nodes, packaging has become a design variable. Chiplets — discrete dies with specialised functions assembled into a single package — allow a system integrator to combine, for example, a leading-edge compute die with a mature-node analogue or I/O die.

The enabling standard is Universal Chiplet Interconnect Express (UCIe), established in 2022 by a consortium including Intel, AMD, Arm, TSMC, Samsung and others. The UCIe 3.0 specification, released on 5 August 2025, raised the maximum supported data rate to 64 GT/s, roughly double UCIe 2.0, and added manageability and runtime recalibration features.

In embedded and automotive contexts, the relevant activity is largely pre-production. imec's Automotive Chiplet Program, launched in late 2024, brings together silicon vendors, tier-one suppliers and OEMs to address the automotive-specific gaps: known-good-die testing, thermal cycling qualification, functional-safety decomposition across dies, and long-term supply of individual chiplets. Arm's Chiplet System Architecture addresses the complementary software and system-partitioning question.

An honest assessment: chiplets solve genuine cost and modularity problems for high-end automotive compute, and first production programmes are anticipated in the late 2020s. Broad multi-vendor mix-and-match integration remains a 2030s expectation. For the majority of embedded designs — a sensor node, a motor controller, an appliance board — chiplets are not, and may never be, economically relevant.

Figure 1 — Suggested diagram: Monolithic MCU versus chiplet-based automotive compute

Purpose: Show why disaggregation is attractive for high-end automotive compute and why it is not for a conventional MCU. Layout: Two side-by-side panels sharing a common legend. Left panel — "Monolithic MCU": A single rounded rectangle labelled "Single die — 40 nm" containing five internal blocks: CPU cores, eFlash, SRAM, Analogue & I/O, Safety island. Caption beneath: "One process node must satisfy every requirement." Right panel — "Chiplet package": An outer rectangle labelled "Package substrate / interposer" containing four separate dies with distinct fills: Compute die (5 nm), NPU die (7 nm), I/O + analogue die (22 nm), Safety MCU die (28 nm, eMRAM). Bidirectional arrows between dies labelled "UCIe die-to-die link". Caption beneath: "Each function uses the node that suits it." Legend: Colour key mapping fill colours to process nodes. Caption: "Figure 1: Disaggregation lets designers match each function to an appropriate process node, at the cost of packaging complexity, test strategy and qualification effort."

Supply chain, mature nodes and industrial policy

Embedded professionals must read semiconductor market data carefully, because aggregate figures now describe a market they do not participate in.

World Semiconductor Trade Statistics reported global semiconductor sales of USD 791.7 billion in 2025, up 25.6% year on year, and its spring 2026 forecast projected roughly USD 1.5 trillion for 2026, with a further rise toward approximately USD 1.9 trillion in 2027. Critically, that acceleration is driven overwhelmingly by the memory segment — forecast to grow by a factor of several times year on year — and by AI-related logic. It says very little about microcontroller demand.

The embedded picture through 2025 and into 2026 was different and more volatile. Analyst reporting through late 2025 described elevated supplier-held inventories in analogue, discrete and MCU categories following the post-shortage correction. That correction suppressed investment in additional mature-node capacity precisely when AI-driven demand began absorbing wafer starts, packaging capacity and substrate supply. Several industry observers in 2026 have reported renewed tightening in specific automotive-grade and high-performance industrial MCU families while commodity 8-bit and legacy 32-bit parts remained readily available. These are segment-level observations from distribution and analyst sources rather than audited data, and readers should treat them as directional signals for procurement planning rather than established facts.

Industrial policy is now a structural feature of this landscape. The European Commission adopted its Chips Act 2.0 proposal on 3 June 2026, building on the 2023 European Chips Act, which the Commission states mobilised more than EUR 52 billion in public and private investment. The revised framework emphasises demand-side measures, faster permitting — with a stated maximum approval period of 12 months — and targeted "Grand Challenges" for strategically important chip categories. A Commission official indicated at the time of publication that the EU does not intend to replicate the United States' approach of taking direct equity stakes in companies. As a legislative proposal, Chips Act 2.0 is subject to negotiation and amendment; its final form is not yet settled.

Safety and security have become silicon requirements

Two regulatory currents now shape embedded semiconductor selection directly.

Functional safety. ISO 26262 governs road-vehicle electrical and electronic systems, with Automotive Safety Integrity Levels from ASIL A to ASIL D; IEC 61508 provides the equivalent framework for industrial systems. Compliance is not achievable by firmware alone: it requires silicon features such as lockstep cores, ECC-protected memories, built-in self-test, and vendor-supplied safety manuals and FMEDA data.

Cybersecurity. The EU Cyber Resilience Act (Regulation (EU) 2024/2847) entered into force on 10 December 2024. Its Article 14 reporting obligations apply from 11 September 2026, requiring manufacturers of products with digital elements to submit an early warning within 24 hours of becoming aware of an actively exploited vulnerability or severe incident, a fuller notification within 72 hours, and a final report thereafter, via a Single Reporting Platform accessible to national CSIRTs and ENISA. The Act's main obligations — secure-by-design requirements, vulnerability handling, technical documentation and CE marking — apply from 11 December 2027. Penalties for non-compliance with essential requirements can reach EUR 15 million or 2.5% of worldwide annual turnover, whichever is higher. The Commission published practical implementation guidance on 27 July 2026.

The silicon implication is direct. Meeting these obligations over a fifteen-year product life requires hardware roots of trust, secure boot, cryptographic acceleration sized for post-quantum migration, sufficient flash headroom for signed updates, and hardware key storage. Sector-specific regimes — UNECE R155 and R156 for vehicle cybersecurity and software updates, IEC 62443 for industrial automation — impose parallel demands.

Figure 2 — Suggested diagram: Compliance-driven silicon requirements pipeline

Purpose: Map regulatory obligations onto concrete hardware features. Layout: Left-to-right flow with three columns and connecting arrows. Column 1 — "Obligation": Stacked boxes: ISO 26262 ASIL-D, IEC 61508 SIL 3, EU CRA Art. 14 (from 11 Sep 2026), EU CRA main obligations (from 11 Dec 2027), UNECE R155/R156. Column 2 — "Derived requirement": Fault detection & diagnostic coverage, Vulnerability detection & reporting process, Secure update over product life, Component transparency (SBOM). Column 3 — "Silicon feature": Lockstep CPU cores, ECC on flash and SRAM, Hardware root of trust / secure boot, Crypto accelerator + key storage, A/B flash partitioning headroom, Immutable device identity. Arrows: Many-to-many, from obligations to requirements to features; use line weight to indicate strength of dependency. Caption: "Figure 2: Regulatory obligations translate into specific, non-optional silicon capabilities that must be selected at the architecture stage, not retrofitted."

Latest developments

Dated items relevant to embedded semiconductor professionals. Established facts and company announcements are distinguished from forecasts.

5 August 2025 — UCIe 3.0 published. Confirmed specification release adding 48 and 64 GT/s data rates and manageability enhancements. Established.
11 September 2026 — EU CRA reporting obligations take effect. Fixed statutory date under Regulation (EU) 2024/2847. Established.
10–12 March 2026 — Embedded World 2026, Nuremberg. Industry reporting from the event described RISC-V's shift from evaluation toward certified design-in, Infineon's pre-silicon toolchain support for a forthcoming AURIX RISC-V MCU family, and the tenth anniversary of the Zephyr RTOS project with support spanning several hundred boards across multiple architectures. Company announcements and event reporting; product availability dates remain vendor-dependent.
3 June 2026 — European Commission adopts Chips Act 2.0 proposal. Established as a legislative proposal; content subject to change during negotiation.
June 2026 — WSTS spring forecast revision. Global 2026 sales projected at roughly USD 1.5 trillion, driven principally by memory. Forecast, not outcome.
27 July 2026 — European Commission publishes CRA implementation guidance. Established.
Ongoing — imec Automotive Chiplet Program. Continues to expand membership and hold industry forums on automotive chiplet standardisation. Established as a research programme; production deployment timelines are forecasts.

Frequently misunderstood concepts and common myths

"Smaller nodes are always better." For embedded parts, smaller nodes raise mask cost, complicate analogue integration and remove eFlash from the menu. Node selection should follow the functional requirement, not fashion.

"RISC-V is free, so it is cheaper." The ISA specification carries no licence fee. Core implementations, verification IP, safety certification, toolchain support and long-term maintenance are not free. Total cost of ownership frequently dominates licence cost.

"TOPS measures AI performance." It measures peak theoretical arithmetic throughput. Delivered performance depends on memory bandwidth, operator coverage and compiler quality.

"Chiplets will replace MCUs." Chiplets address high-end heterogeneous compute. The economics do not favour disaggregating a USD 2 controller.

"An MCU shortage means all MCUs are scarce." Shortages are segment-specific. Automotive-grade and high-performance industrial families behave very differently from commodity 8-bit parts.

"Security can be added in firmware later." Roots of trust, key storage and secure-boot capability are silicon properties. Retrofitting them is generally impossible.

Practical takeaways

For hardware and system architects

Treat non-volatile memory technology as a first-order architectural decision, not a datasheet line item. If your roadmap crosses 22 nm, plan for eMRAM or RRAM behaviour.
Specify safety and security features at the concept stage: lockstep cores, memory ECC, hardware root of trust, and flash headroom for signed A/B updates across the full product life.
Where an NPU is under consideration, gate the decision on your own quantised model measured end-to-end, not on vendor throughput claims.

For firmware and software teams 4. Build a software bill of materials and vulnerability-monitoring process now; CRA reporting obligations apply from 11 September 2026 and reach products already on the market. 5. If evaluating RISC-V, assess the toolchain and safety-certification path with the same rigour as the core itself, and document any reliance on vendor-specific instruction extensions.

For procurement and supply-chain professionals 6. Analyse exposure at part-family level rather than by category. "MCU risk" is not a meaningful unit of analysis. 7. Where feasible, qualify a second source at design time; late qualification of an alternative part in a safety-certified product is expensive and slow. 8. Ask suppliers for written longevity commitments and, for critical parts, an understanding of the fab and packaging locations involved.

For technical leaders and product managers 9. Separate market signals: aggregate semiconductor growth figures in 2025–2026 largely reflect memory and AI, not embedded demand. 10. Budget compliance engineering as a recurring product cost, not a one-off certification event.

Key insights

Embedded semiconductors are a mature-node business governed by cost, analogue performance, temperature and longevity — not transistor density.
Embedded NOR flash has effectively ceased scaling below approximately 28 nm, making eMRAM and RRAM the enabling technologies for advanced-node MCUs.
eMRAM offers superior endurance and back-end integration; eFlash retains advantages in harsh-environment retention and mature-node cost.
RISC-V has achieved production credibility in embedded and automotive roles, backed institutionally through the Quintauris joint venture and vendor roadmaps.
Arm remains dominant in application-class embedded processing; a dual-architecture market is the realistic near-term outcome.
NPUs are becoming a segmentation axis for MCU and MPU families, but vendor TOPS figures are unreliable procurement inputs.
UCIe 3.0, released 5 August 2025, doubled peak die-to-die data rates; automotive chiplet adoption is a late-decade proposition.
WSTS projected roughly USD 1.5 trillion in 2026 global semiconductor sales, but the growth is memory- and AI-led and does not describe embedded demand.
The EU Cyber Resilience Act converts cybersecurity into a product-conformity requirement, with reporting from 11 September 2026 and full obligations from 11 December 2027.
Supply-chain resilience and regulatory compliance now shape silicon selection as strongly as clock speed or memory size.

Frequently asked questions

What is an embedded semiconductor? A chip designed to perform a dedicated function within a larger product rather than serve as a general-purpose computer. The category includes microcontrollers, embedded SoCs, sensor front ends, power management devices and mixed-signal ICs.

What process node are most microcontrollers built on? Most shipping MCUs use mature nodes between roughly 40 nm and 180 nm, with high-performance automotive and industrial families at 28 nm and, increasingly, 22 nm or 16 nm.

Why can't embedded flash memory scale below 28 nm? Its bit-cell structure requires high programming voltages and additional mask layers that become disproportionately costly and difficult to integrate with baseline CMOS logic at smaller geometries.

What is replacing embedded flash? Principally embedded STT-MRAM and RRAM, both fabricated in the back end of line, which adds fewer process steps than eFlash integration.

Is eMRAM production-ready? Yes, at selected foundries and in selected products. Published research demonstrates 22 nm macros with fast random read access at elevated temperatures, and multiple foundries offer eMRAM process options. Qualification requirements remain product-specific.

Is RISC-V ready for safety-critical automotive use? Certified RISC-V cores targeting high ASIL levels have been announced and licensed, and major automotive suppliers have committed to the architecture. Broad production deployment in safety-critical roles is emerging rather than complete.

Does RISC-V eliminate licensing costs? The ISA specification is open, but commercial core implementations, verification IP, safety certification and toolchain support carry cost. Savings are real but smaller than often assumed.

Should I choose Arm or RISC-V for a new embedded design? Decide on ecosystem, certification path and long-term supply rather than ISA ideology. Arm currently offers broader mature tooling and middleware; RISC-V offers extensibility and supplier diversity, with a narrower but rapidly growing ecosystem.

What is an NPU in a microcontroller? A dedicated accelerator for neural-network operations, typically optimised for 8-bit integer arithmetic, that improves inference energy efficiency relative to executing the same model on a general-purpose core.

How should I benchmark edge AI silicon? Measure end-to-end latency and energy per inference using your own quantised model, verify operator coverage, and consult MLPerf Tiny results as an independent reference point.

What is UCIe? Universal Chiplet Interconnect Express, an open standard defining die-to-die connectivity within a package. Version 3.0, published on 5 August 2025, supports data rates up to 64 GT/s.

Are chiplets relevant to ordinary embedded products? Rarely. Chiplets address high-end heterogeneous compute where monolithic integration is prohibitively expensive. Most embedded designs remain better served by monolithic parts.

What does the EU Cyber Resilience Act require of embedded manufacturers? From 11 September 2026, reporting of actively exploited vulnerabilities and severe incidents within defined timeframes. From 11 December 2027, full conformity requirements including secure-by-design measures, vulnerability handling, documentation and CE marking.

Does the CRA apply to products already on the market? The reporting obligations reach products still made available on the EU market on or after 11 September 2026, including those shipped previously. Detailed scope questions require product-specific legal analysis.

Why do MCU shortages keep recurring? Mature-node capacity investment is economically unattractive relative to leading-edge and memory capacity, so supply responds slowly to demand swings. The result is a cycle of correction and re-tightening concentrated in specific part families.

What does ASIL D mean? The highest Automotive Safety Integrity Level under ISO 26262, applied to functions whose failure carries the greatest severity, exposure and lowest controllability. It imposes the most demanding requirements on hardware fault metrics and development process.

Glossary

AEC-Q100 — Automotive Electronics Council stress-qualification standard for integrated circuits, defining temperature grades from Grade 3 to Grade 0.
ASIL — Automotive Safety Integrity Level, the risk classification scheme defined in ISO 26262 (levels A to D).
Chiplet — A discrete die performing a subset of system functions, assembled with others in a single package.
eFlash — Embedded NOR flash memory integrated on the same die as logic.
eMRAM — Embedded magnetoresistive RAM, typically spin-transfer-torque, integrated in the back end of line.
ENISA — The European Union Agency for Cybersecurity.
FMEDA — Failure Modes, Effects and Diagnostic Analysis, a quantitative safety analysis method.
ISA — Instruction Set Architecture, the contract between hardware and compiled software.
Lockstep cores — Two CPU cores executing identical instruction streams with output comparison for fault detection.
Mature node — A well-established process generation, typically 22 nm and above, used for the majority of embedded and analogue devices.
NPU — Neural Processing Unit, an accelerator for machine-learning inference.
RRAM — Resistive RAM, a non-volatile memory based on programmable resistance states.
SBOM — Software Bill of Materials, a machine-readable inventory of software components.
TOPS — Tera-operations per second, a measure of peak arithmetic throughput.
UCIe — Universal Chiplet Interconnect Express, an open die-to-die interconnect standard.

References

Standards and specifications

International Organization for Standardization. (2018). ISO 26262:2018 — Road vehicles: Functional safety. ISO. https://www.iso.org/standard/68383.html
International Electrotechnical Commission. (2010). IEC 61508:2010 — Functional safety of electrical/electronic/programmable electronic safety-related systems. IEC. https://webstore.iec.ch/publication/5515
International Electrotechnical Commission. (2018). IEC 62443 series — Security for industrial automation and control systems. IEC. https://www.iec.ch/blog/understanding-iec-62443
UCIe Consortium. (2025). Universal Chiplet Interconnect Express (UCIe) specification 3.0. https://www.uciexpress.org/specifications
RISC-V International. (n.d.). RISC-V specifications. https://riscv.org/technical/specifications/

Government and regulatory sources

European Parliament and Council of the European Union. (2024). Regulation (EU) 2024/2847 on horizontal cybersecurity requirements for products with digital elements (Cyber Resilience Act). Official Journal of the European Union. https://eur-lex.europa.eu/eli/reg/2024/2847/oj
European Commission. (2026, June 8). Cyber Resilience Act — Reporting obligations. Shaping Europe's Digital Future. https://digital-strategy.ec.europa.eu/en/policies/cra-reporting
European Commission. (2026, June 3). Chips Act 2.0. Shaping Europe's Digital Future. https://digital-strategy.ec.europa.eu/en/policies/chips-act-2
Bureau of Industry and Security, U.S. Department of Commerce. (2024, December). Public report on the use of mature-node semiconductors. https://www.bis.gov/media/documents/public-report-use-mature-node-semiconductors-december-2024

Industry data and reports

Semiconductor Industry Association. (2026, June 5). Global semiconductor sales increase 11% month-to-month in April. https://www.semiconductors.org/global-semiconductor-sales-increase-11-month-to-month-in-april/
World Semiconductor Trade Statistics. (2026). WSTS spring 2026 semiconductor market forecast. https://www.wsts.org/76/Recent-News-Release
Deloitte. (2026). 2026 semiconductor industry outlook. Deloitte Insights. https://www.deloitte.com/us/en/insights/industry/technology/technology-media-telecom-outlooks/semiconductor-industry-outlook.html

Technical documentation and research programmes

imec. (n.d.). Automotive Chiplet Program and Automotive Chiplet Forum. https://www.imec-int.com/en/events/automotive-chiplet-forum
Arm. (2025, April 10). Why chiplets are key to next-gen software-defined vehicles. Arm Newsroom. https://newsroom.arm.com/blog/arm-imec-automotive-chiplets
Synopsys. (2023). Future microcontrollers need embedded MRAM (eMRAM). https://www.synopsys.com/articles/future-nvm-memories.html
MLCommons. (n.d.). MLPerf Tiny benchmark. https://mlcommons.org/benchmarks/inference-tiny/
UCIe Consortium. (2025, August 5). UCIe Consortium introduces 3.0 specification with 64 GT/s performance and enhanced manageability [Press release]. https://www.uciexpress.org/

Industry and trade press

RISC-V International. (2026, March 4). Production-ready, automotive-grade, AI-native: RISC-V at Embedded World 2026. https://riscv.org/blog/embedded-world-2026/
Moor Insights & Strategy. (2026, March 13). Embedded World 2026 — 10 strategic trends driving embedded systems. Forbes. https://www.forbes.com/sites/moorinsights/2026/03/13/embedded-world-2026---10-strategic-trends-driving-embedded-systems/
EE Times. (2026, June 5). Chips Act 2.0 puts demand at center of Europe's semiconductor strategy. https://www.eetimes.com/chips-act-2-0-puts-demand-at-center-of-europes-semiconductor-strategy/
Semiconductor Engineering. (2023, August 15). MRAM getting more attention at smallest nodes. https://semiengineering.com/mram-getting-more-attention-at-smallest-nodes/
Coughlin, T. (2026, January 2). Digital storage and memory projections for 2026, part 2. Forbes. https://www.forbes.com/sites/tomcoughlin/2026/01/02/digital-storage-and-memory-projections-for-2026-part-2/

Editorial note: This article is based on published documentation, standards texts, official regulatory sources and industry reporting. It does not claim first-hand access to unpublished vendor roadmaps or proprietary test data. Where evidence is preliminary, forecast-based or drawn from company announcements, this is stated in the text.